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| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-11-21 15:22:48 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-11-21 15:22:48 +0100 |
| commit | 5abeedad7273a5a99de1aeb40e996b40f8e23811 (patch) | |
| tree | 798cfa0757f6f0e2526af31d77e71c962d515706 /Documentation | |
| parent | 41289b4834c8542075a3955bfaa7b455e3345439 (diff) | |
| parent | c9243d6df0d617535e842aa4c3d1d7dfdb91d07b (diff) | |
Merge tag 'fpga-for-6.19-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga into char-misc-next
Xu writes:
FPGA Manager changes for 6.17-rc1
- Matthew hands over the maintainership of Intel MAX10 BMC secure
update to Yilun.
- Fabio adds missing spi_device_id table for xilinx-spi
- Dihn updates link for Altera & AMD's dt-bindings.
- Andy uses pci_find_vsec_capability() instead of open-codes for
altera-cvp.
All patches have been reviewed on the mailing list, and have been in the
last linux-next releases (as part of our for-next branch).
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
* tag 'fpga-for-6.19-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga:
fpga: altera-cvp: Use pci_find_vsec_capability() when probing FPGA device
dt-bindings: fpga: update link for Altera's and AMD partial recon
fpga: xilinx-spi: Add missing spi_device_id table
MAINTAINERS: change maintainer for Intel MAX10 BMC secure updates
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/fpga/fpga-region.yaml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.yaml b/Documentation/devicetree/bindings/fpga/fpga-region.yaml index 7d2d3b7aa4b7..98e7c311c0c8 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.yaml +++ b/Documentation/devicetree/bindings/fpga/fpga-region.yaml @@ -215,9 +215,9 @@ description: | FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. -- - [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf + [1] https://www.intel.com/programmable/technical-pdfs/683404.pdf [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf - [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf + [3] https://docs.amd.com/v/u/en-US/ug702 properties: $nodename: |