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| author | Catalin Marinas <catalin.marinas@arm.com> | 2026-04-20 13:12:35 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2026-04-20 13:12:35 +0100 |
| commit | 858fbd7248bd84b2899fb2c29bc7bc2634296edf (patch) | |
| tree | 879b4b3a05bc4c6f452212373d5d03a10a25a755 /Documentation | |
| parent | 818f644ec6cbe00a3cddc767b6316e2f527ae865 (diff) | |
| parent | 0baba94a9779c13c857f6efc55807e6a45b1d4e4 (diff) | |
Merge branch 'for-next/c1-pro-erratum-4193714' into for-next/core
* for-next/c1-pro-erratum-4193714:
: Work around C1-Pro erratum 4193714 (CVE-2026-0995)
arm64: errata: Work around early CME DVMSync acknowledgement
arm64: cputype: Add C1-Pro definitions
arm64: tlb: Pass the corresponding mm to __tlbi_sync_s1ish()
arm64: tlb: Introduce __tlbi_sync_s1ish_{kernel,batch}() for TLB maintenance
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/arch/arm64/silicon-errata.rst | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index 65ed6ea33751..8c7ef3a5629d 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -202,6 +202,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V3AE | #3312417 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | C1-Pro | #4193714 | ARM64_ERRATUM_4193714 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | ARM_SMMU_MMU_500_CPRE_ERRATA| | | | #562869,1047329 | | +----------------+-----------------+-----------------+-----------------------------+ |