Merge tag 'mailbox-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox

Pull mailbox updates from Jassi Brar:
 "Platform and core updates

  PCC:
   - Updates to transmission and interrupt handling, including dynamic
     txdone configuration, ->last_tx_done() wiring, and SHMEM
     initialization fixes. Reverted previous shared buffer patch

  MediaTek
   - Introduce mtk-vcp-mailbox driver and bindings for MT8196 VCP
   - Expand mtk-cmdq for MT8196 with GCE virtualization, mminfra_offset,
     and instruction generation data

  Spreadtrum (SPRD)
   - Add Mailbox Revision 2 support and UMS9230 bindings
   - Fix unhandled interrupt masking and TX done delivery flags

  Microchip
   - Add pic64gx compatibility to MPFS
   - Fix out-of-bounds access and smatch warnings in mchp-ipc-sbi

  Core & Misc Platform Updates
   - Prevent out-of-bounds access in fw_mbox_index_xlate()
   - Add bindings for Qualcomm CPUCP (Kaanapali)
   - Simplify mtk-cmdq and zynqmp-ipi with scoped OF child iterators
   - Consolidate various minor fixes, dead code removal, and typo
     corrections across Broadcom, NXP, Samsung, Xilinx, ARM, and core
     headers"

* tag 'mailbox-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: (34 commits)
  mailbox: sprd: mask interrupts that are not handled
  mailbox: sprd: add support for mailbox revision 2
  mailbox: sprd: clear delivery flag before handling TX done
  dt-bindings: mailbox: sprd: add compatible for UMS9230
  mailbox: bcm-ferxrm-mailbox: Use default primary handler
  mailbox: Remove mailbox_client.h from controller drivers
  mailbox: zynqmp-ipi: Simplify with scoped for each OF child loop
  mailbox: mtk-cmdq: Simplify with scoped for each OF child loop
  dt-bindings: mailbox: xlnx,zynqmp-ipi-mailbox: Document msg region requirement
  mailbox: Improve RISCV_SBI_MPXY_MBOX guidance
  mailbox: mchp-ipc-sbi: fix uninitialized symbol and other smatch warnings
  mailbox: arm_mhuv3: fix typo in comment
  mailbox: cix: fix typo in error message
  mailbox: imx: Skip the suspend flag for i.MX7ULP
  mailbox: exynos: drop unneeded runtime pointer (pclk)
  mailbox: pcc: Remove spurious IRQF_ONESHOT usage
  mailbox: mtk-cmdq: Add driver data to support for MT8196
  mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction
  mailbox: mtk-cmdq: Add GCE hardware virtualization configuration
  mailbox: mtk-cmdq: Add cmdq private data to cmdq_pkt for generating instruction
  ...

4 files changed, 66 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml
new file mode 100644
index 000000000000..7b1c5165e64e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-vcp-mbox.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-vcp-mbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Video Companion Processor (VCP) mailbox
+
+maintainers:
+  - Jjian Zhou <Jjian.Zhou@mediatek.com>
+
+description:
+  The MTK VCP mailbox enables the SoC to communicate with the VCP by passing
+  messages through 64 32-bit wide registers. It has 32 interrupt vectors in
+  either direction for signalling purposes.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8196-vcp-mbox
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  "#mbox-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    mailbox@31b80000 {
+        compatible = "mediatek,mt8196-vcp-mbox";
+        reg = <0x31b80000 0x1000>;
+        interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH 0>;
+        #mbox-cells = <0>;
+    };
diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
index 1332aab9a888..5f2ec74c1b29 100644
--- a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
@@ -11,7 +11,11 @@ maintainers:
 
 properties:
   compatible:
-    const: microchip,mpfs-mailbox
+    oneOf:
+      - items:
+          - const: microchip,pic64gx-mailbox
+          - const: microchip,mpfs-mailbox
+      - const: microchip,mpfs-mailbox
 
   reg:
     oneOf:
diff --git a/Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml
index b526f9c0c272..bf6ab4e7050c 100644
--- a/Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/sprd-mailbox.yaml
@@ -16,6 +16,7 @@ properties:
     enum:
       - sprd,sc9860-mailbox
       - sprd,sc9863a-mailbox
+      - sprd,ums9230-mailbox
 
   reg:
     items:
diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
index 04d6473d666f..a5205ee5ad0f 100644
--- a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
@@ -11,6 +11,17 @@ description: |
   messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
   agent owns registers used for notification and buffers for message.
 
+  For Versal devices, there are two types of IPI channels:
+    - Buffered channels: Support message passing and require the "msg"
+    register region to be present on both the host and remote IPI agents.
+    - Buffer-less channels: Support notification only and do not require the
+    "msg" register region. For these channels, the "msg" region should be
+    omitted.
+
+  For message passing, both the host and remote IPI agents must define the "msg"
+  register region. If either agent omits the "msg" region, only notification
+  based communication is possible.
+
                +-------------------------------------+
                | Xilinx ZynqMP IPI Controller        |
                +-------------------------------------+