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authorMatt Turner <mattst88@gmail.com>2026-10-18 10:22:04 -0400
committerMagnus Lindholm <linmag7@gmail.com>2026-10-18 20:09:29 +0200
commit9280e99d87ddd8c6c7fd83f9ea1585967b3dcd60 (patch)
treeecab6de91c4b4dea9ad37e9f7dcf4b85e42e3a3e /arch/alpha/include/uapi
parentc5280a56dc4cbcbbfd3256a0fd58071587e928b0 (diff)
alpha: add HAVE_PERF_REGS and HAVE_PERF_USER_STACK_DUMP support
Let perf sample registers and dump the user stack, which is what the perf tool needs for --call-graph dwarf. The register indices follow the hardware numbering, so r0-r30 map directly to DWARF register numbers, with pc after them. r9-r15 are callee-saved and live in switch_stack rather than pt_regs, so they cannot be sampled. Without r15 an unwinder cannot recover the CFA of a first frame that uses $15 as its frame pointer. sp is not in pt_regs either: for user frames it comes from user_stack_pointer(), and for kernel frames (PERF_SAMPLE_REGS_INTR) it is the end of the trap frame, as in stacktrace.c. Software events such as context switches and tracepoints hand perf a per-CPU pt_regs filled in by perf_fetch_caller_regs() instead of a trap frame. It is not on the stack and has no room for sp, so report sp as 0 there rather than the address of the per-CPU buffer. Assisted-by: Claude:claude-opus-5-5 Acked-by: Ian Rogers <irogers@google.com> Tested-by: Magnus Lindholm <linmag7@gmail.com> Reviewed-by: Magnus Lindholm <linmag7@gmail.com> Signed-off-by: Matt Turner <mattst88@gmail.com> Link: https://lore.kernel.org/r/20261018-alpha-perf-regs-v3-v3-4-52be85332c57@gmail.com Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
Diffstat (limited to 'arch/alpha/include/uapi')
-rw-r--r--arch/alpha/include/uapi/asm/perf_regs.h45
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/alpha/include/uapi/asm/perf_regs.h b/arch/alpha/include/uapi/asm/perf_regs.h
new file mode 100644
index 000000000000..b6d2dcf6e184
--- /dev/null
+++ b/arch/alpha/include/uapi/asm/perf_regs.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _ASM_ALPHA_PERF_REGS_H
+#define _ASM_ALPHA_PERF_REGS_H
+
+/*
+ * Indices 0-30 match the hardware (and DWARF) register numbers.
+ * r9-r15 are not saved in pt_regs and cannot be sampled.
+ */
+enum perf_event_alpha_regs {
+ PERF_REG_ALPHA_R0,
+ PERF_REG_ALPHA_R1,
+ PERF_REG_ALPHA_R2,
+ PERF_REG_ALPHA_R3,
+ PERF_REG_ALPHA_R4,
+ PERF_REG_ALPHA_R5,
+ PERF_REG_ALPHA_R6,
+ PERF_REG_ALPHA_R7,
+ PERF_REG_ALPHA_R8,
+ PERF_REG_ALPHA_R9,
+ PERF_REG_ALPHA_R10,
+ PERF_REG_ALPHA_R11,
+ PERF_REG_ALPHA_R12,
+ PERF_REG_ALPHA_R13,
+ PERF_REG_ALPHA_R14,
+ PERF_REG_ALPHA_R15,
+ PERF_REG_ALPHA_R16,
+ PERF_REG_ALPHA_R17,
+ PERF_REG_ALPHA_R18,
+ PERF_REG_ALPHA_R19,
+ PERF_REG_ALPHA_R20,
+ PERF_REG_ALPHA_R21,
+ PERF_REG_ALPHA_R22,
+ PERF_REG_ALPHA_R23,
+ PERF_REG_ALPHA_R24,
+ PERF_REG_ALPHA_R25,
+ PERF_REG_ALPHA_R26,
+ PERF_REG_ALPHA_R27,
+ PERF_REG_ALPHA_R28,
+ PERF_REG_ALPHA_GP,
+ PERF_REG_ALPHA_SP,
+ PERF_REG_ALPHA_PC,
+ PERF_REG_ALPHA_MAX,
+};
+
+#endif /* _ASM_ALPHA_PERF_REGS_H */