diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2010-08-02 12:52:22 -0700 |
|---|---|---|
| committer | Scott Williams <scwilliams@nvidia.com> | 2010-08-02 17:48:35 -0700 |
| commit | f8118de93735b6b957437c548e2f025b25237ffc (patch) | |
| tree | 598f6c12f053c9eeefbdb5ebade8364465e35911 /arch/arm/mach-tegra/headsmp-t2.S | |
| parent | 3a9a23977f0bda9e63c7e13e9cdea23e262db875 (diff) | |
[arm/tegra] Don't try to enable CoreSight on non-running CPUs
On exit from LP2, __enable_coresite_access was called to reset the
CoreSight interface and re-enable access on all CPUs. However, only
CPU0 would actually be running at the time (the other CPU would still
be held in reset). The attempt to unlock CoreSight on the non-running
CPU would cause a stall on the APB bus while the CoreSight access
timed out. The APB stall would cause SLINK DMA receiver overruns.
Rather than attempting to unlock CoreSight access up front for every
CPU, each CPU is now responsible for unlocking it's own access when
it starts up.
Bug 703311
Change-Id: Ie4611423ed72eb1cd0dbc8b7851f7a047bcffa14
Reviewed-on: http://git-master/r/4683
Reviewed-by: Gary King <gking@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Tested-by: Michael Hsu <mhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/headsmp-t2.S')
| -rw-r--r-- | arch/arm/mach-tegra/headsmp-t2.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/headsmp-t2.S b/arch/arm/mach-tegra/headsmp-t2.S index 35d7bf6bf15e..a5a4fb892a1d 100644 --- a/arch/arm/mach-tegra/headsmp-t2.S +++ b/arch/arm/mach-tegra/headsmp-t2.S @@ -136,6 +136,7 @@ ENDPROC(__restart_pllx) ENTRY(tegra_hotplug_startup) setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 bl __invalidate_cpu_state + enable_coresite r1 /* most of the below is a retread of what happens in __v7_setup and * secondary_startup, to get the MMU re-enabled and to branch |