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| author | Otavio Salvador <otavio@ossystems.com.br> | 2019-03-28 10:47:24 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-28 10:47:24 -0300 |
| commit | 0a8ab17689e628c84a666195bfc6ab85d11cf057 (patch) | |
| tree | 01630dc4a6935df99bf7d11d34ff8d384fed86e2 /arch/arm/mm/cache-v7.S | |
| parent | 1e71d8c630cbc0d1f5d762fd019690b5cdb880ae (diff) | |
| parent | 32aca03c2ce868d3412da0bb6ce6798c7bea357e (diff) | |
Merge pull request #46 from toradex/4.9-2.3.x-imx
4.9 2.3.x imx
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index d2dd211f66ee..8bc5b751ad06 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -362,14 +362,16 @@ v7_dma_inv_range: ALT_UP(W(nop)) #endif mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line + addne r0, r0, r2 tst r1, r3 bic r1, r1, r3 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line -1: - mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line - add r0, r0, r2 cmp r0, r1 +1: + mcrlo p15, 0, r0, c7, c6, 1 @ invalidate D / U line + addlo r0, r0, r2 + cmplo r0, r1 blo 1b dsb st ret lr |