diff options
| author | Minjie Zhuang <minjie.zhuang@nxp.com> | 2019-09-06 16:32:27 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:35 +0800 |
| commit | 4cefbf217d0bf6efa6ed4a67b3fc76374eaca292 (patch) | |
| tree | 1e4e32814d7b5ba18bc7048467c94cd9d6af708d /arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi | |
| parent | 596b29d461786e8fdb31b61cc98a12fe53ecb90d (diff) | |
arm64: dts: imx8qm/imx8qxp: Add GPU devices for 8QM/8QXP
Add gpu in device tree:
arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi
arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi
arm64/boot/dts/freescale/imx8qm-mek.dts
arm64/boot/dts/freescale/imx8qm-ss-gpu.dtsi
arm64/boot/dts/freescale/imx8qm.dtsi
arm64/boot/dts/freescale/imx8qxp-ss-gpu.dtsi
arm64/boot/dts/freescale/imx8qxp.dtsi
Signed-off-by: Minjie Zhuang <minjie.zhuang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi new file mode 100644 index 000000000000..0e84e5199a8f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu1.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +gpu1_subsys: bus@54100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x54100000 0x0 0x54100000 0x40000>, + <0x80000000 0x0 0x80000000 0x80000000>, + <0x0 0x0 0x0 0x10000000>; + + gpu_3d1: gpu@54100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x54100000 0x40000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_1_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <800000000>, <1000000000>; + fsl,sc_gpu_pid = <IMX_SC_R_GPU_1_PID0>; + power-domains = <&pd IMX_SC_R_GPU_1_PID0>; + status = "disabled"; + }; +}; |