diff options
| author | Guoniu.zhou <guoniu.zhou@nxp.com> | 2020-03-25 15:38:24 +0800 |
|---|---|---|
| committer | Guoniu.zhou <guoniu.zhou@nxp.com> | 2020-03-27 13:52:27 +0800 |
| commit | f1e4bfdabb26e4a14aa1ddd5d9360c15e9eba576 (patch) | |
| tree | ab73e3876a72079e88274cbdbc1db10500dde0b7 /arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | |
| parent | ec27b618417c8fe8a954068962b084aabe3dd22e (diff) | |
MLK-23315-2: arm64: dts: imx8: add i2c and irqsteer device node for CI_PI ss
Add i2c controller and irqsteer device node for CI_PI subsystem of iMX8QXP
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi index 5dce31da1111..c7be9fdc4df0 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -254,6 +254,22 @@ img_subsys: bus@58000000 { status = "disabled"; }; + irqsteer_parallel: irqsteer@58260000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x58260000 0x1000>; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&clk_dummy>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + status = "disabled"; + }; + gpio0_mipi_csi0: gpio@58222000 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; reg = <0x58222000 0x1000>; @@ -281,6 +297,20 @@ img_subsys: bus@58000000 { status = "disabled"; }; + i2c0_parallel: i2c@58266000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x58266000 0x1000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_parallel>; + clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_PI_0_I2C_0>; + status = "disabled"; + }; + gpio0_mipi_csi1: gpio@58242000 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; reg = <0x58242000 0x1000>; |