diff options
| author | Peter Chen <peter.chen@nxp.com> | 2020-03-27 10:53:28 +0800 |
|---|---|---|
| committer | Peter Chen <peter.chen@nxp.com> | 2020-03-31 10:14:43 +0800 |
| commit | 30ca4c96ea93227ba3823946bd4b97417b2230e1 (patch) | |
| tree | f91dd88d8393f470fc7958aa43095ac272430c1f /arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | |
| parent | e12c785ff32f91e4c64e4ae50376df68ba95d0f4 (diff) | |
MLK-23676-2 ARM64: dts: imx8dxl-ss-conn: change clock output name for USBOTG2 PHY
USBOTG2 PHY's output name should be PHY ipg clock, but not controller
ahb clock, it is aligned with USBOTG1 PHY's output clock.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi index 23c0a012e3af..9fd0757b2c3b 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -74,7 +74,7 @@ bit-offset = <28>; clocks = <&conn_ipg_clk>; - clock-output-names = "usboh3_2_ahb_clk"; + clock-output-names = "usboh3_2_phy_ipg_clk"; power-domains = <&pd IMX_SC_R_USB_1_PHY>; }; |