diff options
| author | Robby Cai <robby.cai@nxp.com> | 2020-04-28 12:29:04 +0800 |
|---|---|---|
| committer | Robby Cai <robby.cai@nxp.com> | 2020-04-30 16:34:05 +0800 |
| commit | 07364a7aa5ca134f17facb177807575eb460d3c6 (patch) | |
| tree | e6abdd5fac9b3d47554a3c708bd0c157a5efc596 /arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts | |
| parent | 2b941dee90bd39d9b367529cefdd657ee1d40ac4 (diff) | |
MLK-23600-2 arm64: dts: imx8mp: set media axi/apb clock to desired value
set media axi clock to 500MHz and apb clock to 200MHz for 4K
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts index 87677156dda2..b23b80664b11 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775.dts @@ -85,14 +85,28 @@ &mipi_csi_0 { clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, - <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; clock-names = "mipi_clk", "axi_root", "apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <500000000>, <200000000>; }; &mipi_csi_1 { clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, - <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; clock-names = "mipi_clk", "axi_root", "apb_root"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <500000000>, <200000000>; }; |