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authorShenwei Wang <shenwei.wang@nxp.com>2023-05-10 15:33:59 -0500
committerAndrejs Cainikovs <andrejs.cainikovs@toradex.com>2024-05-15 17:04:15 +0000
commitf437ddb7191d15c3b5b87c8b848c479da7ae96e2 (patch)
tree2ba3d14e13f02e97d7a353f6b5f749e29375a72b /arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts
parent3a352868cc848a6c6d0557e8d3c6cb878547a9cf (diff)
tty: serial: fsl_lpuart: optimize the timer based EOP logictoradex_5.15-2.2.x-imx
DMA transfer may end prematurely due to the DMA Rx timeout even during an active transfer because a constant timeout does not accurately simulate an EOP (End Of Package) event. This patch uses a timer to simulate the hardware EOP event. The timer should only complete a DMA transfer once the idle period satisfies a specified interval which is baud rate dependent. The problem has been observed with low baud rates but could occur also with high baud rates. Make the DMA Rx timeout baud rate dependent and check the DMA residue count before copying data to the TTY buffer. If the residue count remains unchanged since the last interrupt, that indicates no new data was received. In this case, the DMA should complete as an EOP event. Otherwise, new data was received during the interval and the EOP condition is not met so restart the DMA Rx timeout Upstream-Status: Backport [cf9aa72d2f91defea23fe29b9e8e941bb2486d5c] Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20230510203359.1353469-1-shenwei.wang@nxp.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts')
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