diff options
| author | Robby Cai <robby.cai@nxp.com> | 2020-12-24 20:41:57 +0800 |
|---|---|---|
| committer | Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> | 2021-04-27 10:41:59 +0000 |
| commit | 1ad71e29f5e58bcf3c128ffdce6f4caece0c6768 (patch) | |
| tree | e14e80ae1d39fd695bf2215d1ccbcbf6bf185a77 /arch/arm64/boot/dts/freescale/imx8mp.dtsi | |
| parent | bdb006cad8f3639fe1048d93e4fe23173ed6486a (diff) | |
MLK-23600-2 Update ISP and Dewarp clock and power
update ISP and Dewarp clock and power
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com>
(cherry picked from commit e6031680ba2d67a6961a5da5fc68a913962c66d2)
(cherry picked from commit f5390f2bcbc7cb9fab29605fc2d3cb61373a5800)
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 133a45f22ffe..daac9bbfc22b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1810,8 +1810,10 @@ compatible = "fsl,imx8mp-isp"; reg = <0x32e10000 0x10000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; - clock-names = "isp_root"; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>; @@ -1824,8 +1826,10 @@ compatible = "fsl,imx8mp-isp"; reg = <0x32e20000 0x10000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; - clock-names = "isp_root"; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>; @@ -1838,6 +1842,14 @@ compatible = "fsl,imx8mp-dwe"; reg = <0x32e30000 0x10000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + power-domains = <&ispdwp_pd>; id = <0>; status = "disabled"; }; @@ -1846,6 +1858,14 @@ compatible = "fsl,imx8mp-dwe"; reg = <0x32e30000 0x10000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + clock-names = "core", "axi", "ahb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + assigned-clock-rates = <500000000>, <200000000>; + power-domains = <&ispdwp_pd>; id = <1>; status = "disabled"; }; |