diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2020-11-11 16:53:21 +0800 |
|---|---|---|
| committer | Fancy Fang <chen.fang@nxp.com> | 2020-11-19 13:51:02 +0800 |
| commit | 6a759a0628c13be3d7347fdbeb5721a34eed3bd8 (patch) | |
| tree | f38d442d3488991eb753c20ee1701ff5671e8cf2 /arch/arm64/boot/dts/freescale/imx8mp.dtsi | |
| parent | 1e1f957cda193ece9346f0ef39a95bc52a2877ae (diff) | |
MLK-24998-5 arm64: dts: imx8mp: correct assigned-clock-rates for lcdif2
According to i.MX8MP Architecture Defition Document, the maximum
clock rate comes generated by 'ccm_media_disp2_pix_clk_root' is
160MHz, so 1039.5MHz clock rate is not supported. And besides,
this clock rate will be set to the matched rate with display mode
in lcdif driver, so it is not necessary to set its rate in its
assigned-clock-rates property, and just leave it to be 0.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 0e3556f282466e6b91def024afc815ef77733161)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 496c4c77d3dd..4bb946f10c53 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1478,7 +1478,7 @@ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <1039500000>, <500000000>, <200000000>; + assigned-clock-rates = <0>, <500000000>, <200000000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&mediamix_pd>; status = "disabled"; |