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authorRobby Cai <robby.cai@nxp.com>2021-01-27 21:54:32 +0800
committerAndrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>2021-04-27 10:41:58 +0000
commitbdb006cad8f3639fe1048d93e4fe23173ed6486a (patch)
tree77f50979b1b177311d88207c13621ca05290b3d6 /arch/arm64/boot/dts/freescale/imx8mp.dtsi
parenta687b8a79615654987bd83eb868f4c21a4a8f77d (diff)
MLK-23600-1 Change MIPI CSI clock to 266MHz for dual ISP cameras
Set MIPI clock according to IC team. for 1 ISP camera on CSI0, MIPI CSI clock set to 500MHz for 2 ISP cameras on CSI0/CSI1, MIPI CSI clock both set to 266MHz Signed-off-by: Robby Cai <robby.cai@nxp.com> Reviewed-by: Guoniu.zhou <guoniu.zhou@nxp.com> (cherry picked from commit a38f457b63fa8a0d9b4c5de39a12959c172e7e35) (cherry picked from commit e20ebbce9f06086249d7dda9d73bd9e328074c02) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mp.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 0587b201b83b..133a45f22ffe 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1880,7 +1880,7 @@
<&clk IMX8MP_CLK_MEDIA_APB>;
clock-names = "mipi_clk", "disp_axi", "disp_apb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
assigned-clock-rates = <266000000>;
bus-width = <4>;
csi-gpr = <&mediamix_gasket1>;