diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2019-11-29 16:57:52 +0800 |
|---|---|---|
| committer | Haibo Chen <haibo.chen@nxp.com> | 2019-11-29 17:39:19 +0800 |
| commit | 187d81ea3bf68171a21baf33e6faf2c5df24f341 (patch) | |
| tree | 0b0bb887398f8b688f166a12e8ffa22a7505612c /arch/arm64/boot/dts/freescale/imx8mq.dtsi | |
| parent | d12ea28a22e5217d70ccef8fcdb4c38234ffa418 (diff) | |
LF-270 ARM64: dts: imx8mq.dtsi: set the IMX8MQ_CLK_NAND_USDHC_BUS clock rate
Need to set the IMX8MQ_CLK_NAND_USDHC_BUS clock rate to 266MHz, to make
clock align, otherwise USDHC oparation will has issue.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mq.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index f71ffd231109..5ded5dd003ec 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -623,6 +623,8 @@ clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>; }; src: reset-controller@30390000 { |