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authorLiu Ying <victor.liu@nxp.com>2020-03-30 10:37:34 +0800
committerLiu Ying <victor.liu@nxp.com>2020-04-10 15:24:02 +0800
commit264e4fe116a6b27869f690b9910f16a706acf2e0 (patch)
tree8f2053f123215d12dbc65aaa869688fb9f85384d /arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts
parenta1c49e1eea2dbd5f4683f332949d088a6d60d797 (diff)
LF-1189-15 arm64: imx8qxp-mek: Add Seiko WVGA LCD panel(driven by DPU) support
This patch adds Seiko WVGA LCD panel support on the i.MX8qxp mek platform. The panel is driven by DPU in DC0 subsystem. Reviewed-by: Robert Chiras <robert.chiras@nxp.com> Tested-by: Robert Chiras <robert.chiras@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts77
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts
new file mode 100644
index 000000000000..c8397bb6d456
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-dpu-lcdif.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8qxp-mek-rpmsg.dts"
+
+/ {
+ panel {
+ compatible = "sii,43wvf1g";
+ backlight = <&lcdif_backlight>;
+ status = "okay";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ display@disp1 {
+ compatible = "fsl,imx-lcdif-mux-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>,
+ <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
+ clock-names = "bypass_div", "pixel";
+ assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
+ assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
+ fsl,lcdif-mux-regs = <&lcdif_mux_regs>;
+ fsl,interface-pix-fmt = "rgb666";
+ power-domains = <&pd IMX_SC_R_LCD_0>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&dpu_disp1_lcdif>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+};
+
+&dpu_disp1_lcdif {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&iomuxc {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000
+ >;
+ };
+};
+
+&sai1 {
+ status = "disabled";
+};
+
+&esai0 {
+ status = "disabled";
+};
+
+&lpuart1 {
+ status = "disabled";
+};