diff options
| author | Stoica Cosmin-Stefan <cosmin.stoica@nxp.com> | 2015-06-08 18:55:18 +0300 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:11:40 +0800 |
| commit | 9b260c850164ee5c907b6c90a86d54e1b4ff29fe (patch) | |
| tree | 8cf0d7f8eabe07459a25031c3a389ace0b5e5164 /arch/arm64/boot/dts/freescale/s32v234.dtsi | |
| parent | 6a0eef0672f4f459a2dc063b87e5fab6a18fe27b (diff) | |
arm64: Prepare S32V234 dtsi for clock support
Update device tree with nodes needed by the clock driver, including clock
generation module (MC_CGM), mode entry module (MC_ME) and system reset
controller (SRC).
Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Signed-off-by: Dragoș Papavă <dragos.papava@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/s32v234.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32v234.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index 355009ada915..a57dcc859875 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -20,6 +20,22 @@ serial1 = &uart1; }; + clocks { + #address-cells = <1>; + #size-cells = <0>; + + firc { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + fxosc { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -113,6 +129,17 @@ reg = <0x0 0x40000000 0x0 0x7d000>; ranges; + clks: mc_cgm0@4003c000 { + compatible = "fsl,s32v234-mc_cgm0"; + reg = <0x0 0x4003C000 0x0 0x1000>; + #clock-cells = <1>; + }; + + mc_me: mc_me@4004a000 { + compatible = "fsl,s32v234-mc_me"; + reg = <0x0 0x4004A000 0x0 0x1000>; + }; + uart0: serial@40053000 { compatible = "fsl,s32v234-linflexuart"; reg = <0x0 0x40053000 0x0 0x1000>; @@ -125,6 +152,12 @@ reg = <0x0 0x4006C000 0x0 0x1794>; status = "disabled"; }; + + src: src@4007c000 { + compatible = "fsl,s32v234-src"; + reg = <0x0 0x4007C000 0x0 0x1000>; + #reset-cells = <1>; + }; }; aips1: aips-bus@40080000 { |