diff options
author | Dinh Nguyen <dinguyen@kernel.org> | 2025-06-04 13:44:08 -0500 |
---|---|---|
committer | Dinh Nguyen <dinguyen@kernel.org> | 2025-07-12 07:19:53 -0500 |
commit | cd51991a21e7b4780cac3b17bf5d89d07df13266 (patch) | |
tree | df79c4ab5a4c19cd1a2f7fe9194596b4c2adb4b0 /arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | |
parent | 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 (diff) |
arm64: dts: socfpga: agilex: fix dtbs_check warning for f2s-free-clk
The f2s-free-clk requires a clock-frequency value. We put in an
arbitrary value of 100 MHz for a constant. The true clock frequency
would get generated in an FPGA design and the bootloader will populated
in actual hardware designs.
This fixes warning like this:
arch/arm64/boot/dts/intel:34:8
4 f2s-free-clk (fixed-clock): 'clock-frequency' is a required property
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/intel/socfpga_agilex.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index a77a504effea..c1e66db0f4c5 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -126,6 +126,7 @@ f2s_free_clk: f2s-free-clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <100000000>; }; osc1: osc1 { |