diff options
| author | Swapnil Jakhade <sjakhade@cadence.com> | 2024-06-10 10:41:21 +0200 |
|---|---|---|
| committer | Parth Pancholi <parth.pancholi@toradex.com> | 2024-06-11 15:30:50 +0000 |
| commit | 3b090455bc2b42f4f6333bf01845c0a975bea9f1 (patch) | |
| tree | e283d4e90e8deeed4a4dad687ca9ba8acbfaaf9a /arch/arm64/boot | |
| parent | bedc01a0403c3d210a2f41f8f6dee5eabb89820b (diff) | |
phy: cadence-torrent: Add PCIe multilink + SGMII/QSGMIItoradex_ti-linux-6.1.y
Add register sequences for PCIe multilink + SGMII/QSGMII
configuration for 100MHz reference clock with no SSC.
For Toradex Aquila AM69 SOMs, SERDES1 from AM69 SOC is
intended to support PCIE0 (2 Lane), PCIE2 (1 Lane) and
QSGMII for Aquila PCIE_1, On-module PCIe USB bridge and
Aquila ETH_2 interfaces respectively. This enables the
required support of PCIE multilink and xGMII interfaces
without SSC.
TI shared this change in E2E support forum [1] and not
part of ti-linux-kernel repo yet.
[1]
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1346931/am69-why-pcie2_ep-and-or-pcie2_rc-nodes-are-not-configured-in-main-k3-j784s4-main-dtsi/
Upstream-Status: Pending
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
Diffstat (limited to 'arch/arm64/boot')
0 files changed, 0 insertions, 0 deletions