diff options
| author | Marc Zyngier <maz@kernel.org> | 2025-01-27 11:58:38 +0000 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2025-05-19 11:36:21 +0100 |
| commit | 98dbe56a016a4ea457ef312637a625d3c627dbd9 (patch) | |
| tree | 4db45c40d49bc3852ccd676008eb663aa48dcb17 /arch/arm64/include | |
| parent | af2d78dcadbc2386610566ab2052fee78993fb53 (diff) | |
KVM: arm64: Handle TSB CSYNC traps
The architecture introduces a trap for TSB CSYNC that fits in
the same EC as LS64 and PSB CSYNC. Let's deal with it in a similar
way.
It's not that we expect this to be useful any time soon anyway.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/esr.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index ef5a14276ce1..6079e23608a2 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -182,10 +182,11 @@ #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) -/* ISS definitions for LD64B/ST64B/PSBCSYNC instructions */ +/* ISS definitions for LD64B/ST64B/{T,P}SBCSYNC instructions */ #define ESR_ELx_ISS_OTHER_ST64BV (0) #define ESR_ELx_ISS_OTHER_ST64BV0 (1) #define ESR_ELx_ISS_OTHER_LDST64B (2) +#define ESR_ELx_ISS_OTHER_TSBCSYNC (3) #define ESR_ELx_ISS_OTHER_PSBCSYNC (4) #define DISR_EL1_IDS (UL(1) << 24) |