diff options
| author | Will Deacon <will@kernel.org> | 2023-04-20 18:03:07 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2023-04-20 18:03:07 +0100 |
| commit | eeb3557cc188e42ae7f7bef2d6dc5bf0e078412e (patch) | |
| tree | c46faaaa4a51d477d98c8226f7cc95864fca8aa6 /arch/arm64/include | |
| parent | 9772b7f07499b71482276cb5a8e4aa23bfca6b27 (diff) | |
| parent | bbd329fe723d185485598bf52378a8341912a804 (diff) | |
Merge branch 'for-next/sysreg' into for-next/core
* for-next/sysreg:
arm64/sysreg: Convert HFGITR_EL2 to automatic generation
arm64/idreg: Don't disable SME when disabling SVE
arm64/sysreg: Update ID_AA64PFR1_EL1 for DDI0601 2022-12
arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation
arm64/sysreg: allow *Enum blocks in SysregFields blocks
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9e3ecba3c4e6..c48b41c9b0cc 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -419,9 +419,6 @@ #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3) -#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4) -#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5) -#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6) #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7) #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) @@ -758,12 +755,6 @@ #define ICH_VTR_TDS_SHIFT 19 #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) -/* HFG[WR]TR_EL2 bit definitions */ -#define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55 -#define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT) -#define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54 -#define HFGxTR_EL2_nSMPRI_EL1_MASK BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT) - #define ARM64_FEATURE_FIELD_BITS 4 /* Defined for compatibility only, do not add new users. */ |