diff options
| author | D Scott Phillips <scott@os.amperecomputing.com> | 2025-05-13 11:45:14 -0700 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2025-05-19 12:46:26 +0100 |
| commit | fed55f49fad181be9dfb93c06efc4ab2b71a72a9 (patch) | |
| tree | c9059e72c2dccec0c2e34d5198aa74901a1771da /arch/arm64/kvm/hyp/nvhe/host.S | |
| parent | 92c749e4aa90cd684d87cb5bde6a9d51e83fe6e3 (diff) | |
arm64: errata: Work around AmpereOne's erratum AC04_CPU_23
On AmpereOne AC04, updates to HCR_EL2 can rarely corrupt simultaneous
translations for data addresses initiated by load/store instructions.
Only instruction initiated translations are vulnerable, not translations
from prefetches for example. A DSB before the store to HCR_EL2 is
sufficient to prevent older instructions from hitting the window for
corruption, and an ISB after is sufficient to prevent younger
instructions from hitting the window for corruption.
Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com>
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250513184514.2678288-1-scott@os.amperecomputing.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm64/kvm/hyp/nvhe/host.S')
| -rw-r--r-- | arch/arm64/kvm/hyp/nvhe/host.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kvm/hyp/nvhe/host.S b/arch/arm64/kvm/hyp/nvhe/host.S index 58f0cb2298cc..eef15b374abb 100644 --- a/arch/arm64/kvm/hyp/nvhe/host.S +++ b/arch/arm64/kvm/hyp/nvhe/host.S @@ -124,7 +124,7 @@ SYM_FUNC_START(__hyp_do_panic) /* Ensure host stage-2 is disabled */ mrs x0, hcr_el2 bic x0, x0, #HCR_VM - msr hcr_el2, x0 + msr_hcr_el2 x0 isb tlbi vmalls12e1 dsb nsh |