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authorLorenzo Pieralisi <lpieralisi@kernel.org>2025-07-03 12:24:54 +0200
committerMarc Zyngier <maz@kernel.org>2025-07-08 18:35:50 +0100
commitfb0ad5ed5676f0a8cbee4cd148db1b692bda8a4b (patch)
tree6e927a3015e8aa4908572c9345d66586600cfe5b /arch/arm64/tools/sysreg
parent1bd7238dc705f07dea14040a59378e4b1be7164a (diff)
arm64/sysreg: Add ICC_ICSR_EL1
Add ICC_ICSR_EL1 register sysreg description. Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-4-12e71f1b3528@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm64/tools/sysreg')
-rw-r--r--arch/arm64/tools/sysreg14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index fc17e19a738d..81b32f567ce3 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -3024,6 +3024,20 @@ Sysreg PMIAR_EL1 3 0 9 14 7
Field 63:0 ADDRESS
EndSysreg
+Sysreg ICC_ICSR_EL1 3 0 12 10 4
+Res0 63:48
+Field 47:32 IAFFID
+Res0 31:16
+Field 15:11 Priority
+Res0 10:6
+Field 5 HM
+Field 4 Active
+Field 3 IRM
+Field 2 Pending
+Field 1 Enabled
+Field 0 F
+EndSysreg
+
SysregFields ICC_PPI_PRIORITYRx_EL1
Res0 63:61
Field 60:56 Priority7