diff options
| author | Liu Ying <victor.liu@nxp.com> | 2018-08-02 13:47:10 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | dab218c3c46644215f5709e03729bbe9ba3b5823 (patch) | |
| tree | d6bd159d97303c1ca2f78a85f4e8853d582d9f79 /arch/arm64 | |
| parent | 48158789ac51b03f5fdef509ede769af52a7a873 (diff) | |
MLK-19114-1 arm64: fsl-imx8qm.dtsi: Add aux prg for dpr1/3_channel2
With the updated i.MX8QM silicon, prg1/10 may be shared bewteen
dpr1/3_channel1 and dpr1/3_channel2 respectively with appropriate
mux configurations in SCU firmware. If prg1/10 are attached to
dpr1/3_channel2, then they act as the auxiliary prg to process
chroma pixels for SC_R_DC_0/1_BLIT1. Otherwise, they act as the
primary prg to process RGB pixels for SC_R_DC_0/1_BLIT0.
Let's reflect this update in the device tree file.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index a6f609057b13..9e9fdc388ed9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -1633,7 +1633,7 @@ compatible = "fsl,imx8qm-dpr-channel"; reg = <0x0 0x560e0000 0x0 0x10000>; fsl,sc-resource = <SC_R_DC_0_BLIT1>; - fsl,prgs = <&prg2>; + fsl,prgs = <&prg2>, <&prg1>; clocks = <&clk IMX8QM_DC0_DPR0_APB_CLK>, <&clk IMX8QM_DC0_DPR0_B_CLK>, <&clk IMX8QM_DC0_RTRAM0_CLK>; @@ -2097,7 +2097,7 @@ compatible = "fsl,imx8qm-dpr-channel"; reg = <0x0 0x570e0000 0x0 0x10000>; fsl,sc-resource = <SC_R_DC_1_BLIT1>; - fsl,prgs = <&prg11>; + fsl,prgs = <&prg11>, <&prg10>; clocks = <&clk IMX8QM_DC1_DPR0_APB_CLK>, <&clk IMX8QM_DC1_DPR0_B_CLK>, <&clk IMX8QM_DC1_RTRAM0_CLK>; |