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| author | Thomas Gleixner <tglx@linutronix.de> | 2025-11-22 17:07:57 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2025-11-22 17:07:57 +0100 |
| commit | ebb922c920cefbeb2ce93775a66da0df479661cc (patch) | |
| tree | d1629e2317a08aebd9c351916676054a42e7a6df /arch/csky/abiv2/cacheflush.c | |
| parent | ac646f44956edc9aaa406b4a8fef17888a2166af (diff) | |
| parent | dcb6fa37fd7bc9c3d2b066329b0d27dedf8becaa (diff) | |
Merge tag 'v6.18-rc3' into irq/msi
Pick up OF changes to resolve dependencies
Diffstat (limited to 'arch/csky/abiv2/cacheflush.c')
| -rw-r--r-- | arch/csky/abiv2/cacheflush.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/csky/abiv2/cacheflush.c b/arch/csky/abiv2/cacheflush.c index 876028b1083f..064b0f0f95ca 100644 --- a/arch/csky/abiv2/cacheflush.c +++ b/arch/csky/abiv2/cacheflush.c @@ -21,7 +21,7 @@ void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma, folio = page_folio(pfn_to_page(pfn)); - if (test_and_set_bit(PG_dcache_clean, &folio->flags)) + if (test_and_set_bit(PG_dcache_clean, &folio->flags.f)) return; icache_inv_range(address, address + nr*PAGE_SIZE); |