diff options
| author | Huacai Chen <chenhuacai@loongson.cn> | 2024-07-20 22:40:59 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2024-07-20 22:40:59 +0800 |
| commit | 8e02c3b782ec64343f3cccc8dc5a8be2b379e80b (patch) | |
| tree | b3dea31c724b20becad2cd2a892b304234573457 /arch/loongarch/power/suspend_asm.S | |
| parent | 614d7e99752e02ff6f6d447a83d2929b9649b6cb (diff) | |
LoongArch: Add writecombine support for DMW-based ioremap()
Currently, only TLB-based ioremap() support writecombine, so add the
counterpart for DMW-based ioremap() with help of DMW2. The base address
(WRITECOMBINE_BASE) is configured as 0xa000000000000000.
DMW3 is unused by kernel now, however firmware may leave garbage in them
and interfere kernel's address mapping. So clear it as necessary.
BTW, centralize the DMW configuration to macro SETUP_DMWINS.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/power/suspend_asm.S')
| -rw-r--r-- | arch/loongarch/power/suspend_asm.S | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/loongarch/power/suspend_asm.S b/arch/loongarch/power/suspend_asm.S index e2fc3b4e31f0..c28ad52b7baf 100644 --- a/arch/loongarch/power/suspend_asm.S +++ b/arch/loongarch/power/suspend_asm.S @@ -73,11 +73,7 @@ SYM_FUNC_START(loongarch_suspend_enter) * Reload all of the registers and return. */ SYM_INNER_LABEL(loongarch_wakeup_start, SYM_L_GLOBAL) - li.d t0, CSR_DMW0_INIT # UC, PLV0 - csrwr t0, LOONGARCH_CSR_DMWIN0 - li.d t0, CSR_DMW1_INIT # CA, PLV0 - csrwr t0, LOONGARCH_CSR_DMWIN1 - + SETUP_DMWINS t0 JUMP_VIRT_ADDR t0, t1 /* Enable PG */ |