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authorIngo Molnar <mingo@elte.hu>2009-05-11 09:33:06 +0200
committerIngo Molnar <mingo@elte.hu>2009-05-11 09:50:02 +0200
commit7a309490da98981558a07183786201f02a6341e2 (patch)
tree204bfd3bc344dbb02be0b1eac29b956f6722e661 /arch/microblaze/kernel/cpu/cache.c
parent9a8709d44139748fe2e0ab56d20d8c384c8b65ad (diff)
parent091bf7624d1c90cec9e578a18529f615213ff847 (diff)
Merge commit 'v2.6.30-rc5' into x86/apic
Merge reason: this branch was on a .30-rc2 base - sync it up with all the latest fixes. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/microblaze/kernel/cpu/cache.c')
-rw-r--r--arch/microblaze/kernel/cpu/cache.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index be9fecca4f91..af866a450125 100644
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -100,7 +100,6 @@ void _enable_dcache(void)
void _disable_dcache(void)
{
- if (cpuinfo.use_dcache) {
#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
__asm__ __volatile__ (" \
msrclr r0, %0; \
@@ -119,12 +118,10 @@ void _disable_dcache(void)
: "i" (MSR_DCE) \
: "memory", "r12");
#endif
- }
}
void _invalidate_dcache(unsigned int addr)
{
- if (cpuinfo.use_dcache)
__asm__ __volatile__ (" \
wdc %0, r0" \
: \