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authorThomas Gleixner <tglx@linutronix.de>2016-06-03 15:05:51 +0200
committerThomas Gleixner <tglx@linutronix.de>2016-06-03 15:05:51 +0200
commit2eec3707a33fbf1c2e0a88ffc9fc0e465c2a59fd (patch)
tree9e47763ecd38f0ddd29f07e1ce199680304449fa /arch/mips/mm/page.c
parent59fa5860204ffc95128d60cba9f54f9740a42c7d (diff)
parent0de6b9979e2e10c79e5702d2d902cd7284d17689 (diff)
Merge tag 'irqchip-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Merge irqchip updates from Marc Zyngier: - A number of embarassing buglets (GICv3, PIC32) - A more substential errata workaround for Cavium's GICv3 ITS (kept for post-rc1 due to its dependency on NUMA)
Diffstat (limited to 'arch/mips/mm/page.c')
-rw-r--r--arch/mips/mm/page.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 885d73ffd6fb..c41953ca6605 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -188,6 +188,15 @@ static void set_prefetch_parameters(void)
}
break;
+ case CPU_LOONGSON3:
+ /* Loongson-3 only support the Pref_Load/Pref_Store. */
+ pref_bias_clear_store = 128;
+ pref_bias_copy_load = 128;
+ pref_bias_copy_store = 128;
+ pref_src_mode = Pref_Load;
+ pref_dst_mode = Pref_Store;
+ break;
+
default:
pref_bias_clear_store = 128;
pref_bias_copy_load = 256;