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authorIcenowy Zheng <zhengxingda@iscas.ac.cn>2026-01-02 23:52:43 +0800
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2026-01-30 15:35:26 +0100
commite4ec36bf7bc7023e1d207b1277755b0da381f20f (patch)
tree9a92bd7f17033ce3b8bba768ceec2ab974e9e975 /arch/mips
parent026d70dcfe5de1543bb8edb8e50d22dc16863e6b (diff)
MIPS: Loongson64: dts: fix phy-related definition of LS7A GMAC
Currently the LS7A GMAC device tree node lacks a proper phy-handle property pointing to the PHY node. In addition, the phy-mode property specifies "rgmii" without any internal delay information, which means the board trace needs to add 2ns delay to the RGMII data lines; but that isn't known to happen on any Loongson board. The ACPI-based initialization codepath, which is used on LoongArch-based 3A5000 + 7A1000 hardwares, specifies "rgmii-id" phy mode, which should be the one we are using. Add the lacking phy-handle property and set proper phy-mode. Tested on a LS3A4000_7A1000_NUC_BOARD_V2.1 board with YT8521S PHY. Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/boot/dts/loongson/ls7a-pch.dtsi6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
index ee71045883e7..6dee85909f5a 100644
--- a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -199,7 +199,8 @@
<13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -222,7 +223,8 @@
<15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&pic>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;