diff options
| author | Stafford Horne <shorne@gmail.com> | 2025-12-10 17:08:27 +0000 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2026-01-16 16:38:56 +0000 |
| commit | eea1a28f93c8c78b961aca2012dedfd5c528fcac (patch) | |
| tree | 73032dfac1cb6eead58bce74cc462df9018af17c /arch/openrisc/kernel | |
| parent | 111005cafb53efdaf00436bc678f5372a7e06c55 (diff) | |
openrisc: Fix IPIs on simple multicore systems
Commit c05671846451 ("openrisc: sleep instead of spin on secondary
wait") fixed OpenRISC SMP Linux for QEMU. However, stability was never
achieved on FPGA development boards. This is because the above patch
has a step to unmask IPIs on non-boot cpu's but on hardware without
power management, IPIs remain masked.
This meant that IPI's were never actually working on the simple SMP
systems we run on development boards. The systems booted but stability
was very suspect.
Add the ability to unmask IPI's on the non-boot cores. This is done by
making the OMPIC IRQs proper percpu IRQs. We can then use the
enabled_percpu_irq() to unmask IRQ on the non-boot cpus.
Update the or1k PIC driver to use a flow handler that can switch between
percpu and the configured level or edge flow handlers at runtime.
This mechanism is inspired by that done in the J-Core AIC driver.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Acked-by: Thomas Gleixner <tglx@kernel.org>
Diffstat (limited to 'arch/openrisc/kernel')
| -rw-r--r-- | arch/openrisc/kernel/smp.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c index 86da4bc5ee0b..040ca201b692 100644 --- a/arch/openrisc/kernel/smp.c +++ b/arch/openrisc/kernel/smp.c @@ -13,6 +13,7 @@ #include <linux/smp.h> #include <linux/cpu.h> +#include <linux/interrupt.h> #include <linux/sched.h> #include <linux/sched/mm.h> #include <linux/irq.h> @@ -25,6 +26,7 @@ asmlinkage __init void secondary_start_kernel(void); +static unsigned int ipi_irq __ro_after_init; static void (*smp_cross_call)(const struct cpumask *, unsigned int); unsigned long secondary_release = -1; @@ -39,6 +41,14 @@ enum ipi_msg_type { static DEFINE_SPINLOCK(boot_lock); +static void or1k_ipi_enable(void) +{ + if (WARN_ON_ONCE(!ipi_irq)) + return; + + enable_percpu_irq(ipi_irq, 0); +} + static void boot_secondary(unsigned int cpu, struct task_struct *idle) { /* @@ -136,6 +146,7 @@ asmlinkage __init void secondary_start_kernel(void) complete(&cpu_running); synchronise_count_slave(cpu); + or1k_ipi_enable(); set_cpu_online(cpu, true); local_irq_enable(); @@ -195,9 +206,18 @@ void smp_send_stop(void) smp_call_function(stop_this_cpu, NULL, 0); } -void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) +void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int), + unsigned int irq) { + if (WARN_ON(ipi_irq)) + return; + smp_cross_call = fn; + + ipi_irq = irq; + + /* Enabled IPIs for boot CPU immediately */ + or1k_ipi_enable(); } void arch_send_call_function_single_ipi(int cpu) |