diff options
author | Dave Airlie <airlied@redhat.com> | 2025-05-06 16:39:25 +1000 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2025-05-06 16:39:25 +1000 |
commit | 5e0c67998152bdb91b056160449ee542b86271a5 (patch) | |
tree | dff9fd979b0319dd2ed873a77246950d7ed95ceb /arch/openrisc/mm/init.c | |
parent | 135130db6ee6500e6c82cf44dd831c3fe15f7b5f (diff) | |
parent | 92a09c47464d040866cf2b4cd052bc60555185fb (diff) |
BackMerge tag 'v6.15-rc5' into drm-next
Linux 6.15-rc5, requested by tzimmerman for fixes required in drm-next.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'arch/openrisc/mm/init.c')
-rw-r--r-- | arch/openrisc/mm/init.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c index be1c2eb8bb94..e4904ca6f0a0 100644 --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -35,6 +35,7 @@ #include <asm/fixmap.h> #include <asm/tlbflush.h> #include <asm/sections.h> +#include <asm/cacheflush.h> int mem_init_done; @@ -176,8 +177,8 @@ void __init paging_init(void) barrier(); /* Invalidate instruction caches after code modification */ - mtspr(SPR_ICBIR, 0x900); - mtspr(SPR_ICBIR, 0xa00); + local_icache_block_inv(0x900); + local_icache_block_inv(0xa00); /* New TLB miss handlers and kernel page tables are in now place. * Make sure that page flags get updated for all pages in TLB by |