diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2026-10-05 19:02:53 -0600 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-10-05 19:02:53 -0600 |
| commit | f89e5ee4d8c6cd56499cd87e550d4d4e19cf7e17 (patch) | |
| tree | e51bf556d83b3ba948c8e896f60385cee4e3d937 /arch/riscv/include | |
| parent | 30755e71abb1aa9d1d51ea9fdd6a5c07807c3b40 (diff) | |
riscv: fix RVG_SYSTEM_CSR_MASK width mask
RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits.
Replace GENMASK(12, 0) by GENMASK(11, 0).
Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Link: https://patch.msgid.link/20260911194233.3379532-1-aurelien@aurel32.net
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/insn.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index c3005573e8c9..ad348d8b8857 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -142,7 +142,7 @@ #define RVG_OPCODE_JAL 0x6f #define RVG_OPCODE_SYSTEM 0x73 #define RVG_SYSTEM_CSR_OFF 20 -#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0) +#define RVG_SYSTEM_CSR_MASK GENMASK(11, 0) /* parts of opcode for RVF, RVD and RVQ */ #define RVFDQ_FL_FS_WIDTH_OFF 12 |