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| author | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2017-02-22 07:44:15 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@s-opensource.com> | 2017-02-22 07:44:15 -0300 |
| commit | e6b377dbbb944d5e3ceef4e5d429fc5c841e3692 (patch) | |
| tree | c84b714acad1ad20a0f0ea223dc019dd1267f4b6 /arch/x86/include/asm/microcode_intel.h | |
| parent | 9eeb0ed0f30938f31a3d9135a88b9502192c18dd (diff) | |
| parent | c470abd4fde40ea6a0846a2beab642a578c0b8cd (diff) | |
Merge tag 'v4.10' into patchwork
Linux 4.10
* tag 'v4.10': (1558 commits)
Linux 4.10
Fix missing sanity check in /dev/sg
scsi: don't BUG_ON() empty DMA transfers
ipv6: release dst on error in ip6_dst_lookup_tail
printk: use rcuidle console tracepoint
ARM: multi_v7_defconfig: enable Qualcomm RPMCC
irda: Fix lockdep annotations in hashbin_delete().
vxlan: fix oops in dev_fill_metadata_dst
dccp: fix freeing skb too early for IPV6_RECVPKTINFO
dpaa_eth: small leak on error
packet: Do not call fanout_release from atomic contexts
reset: fix shared reset triggered_count decrement on error
ntb: ntb_hw_intel: link_poll isn't clearing the pending status properly
ntb_transport: Pick an unused queue
ntb: ntb_perf missing dmaengine_unmap_put
NTB: ntb_transport: fix debugfs_remove_recursive
Revert "nohz: Fix collision between tick and other hrtimers"
vfs: fix uninitialized flags in splice_to_pipe()
drm/radeon: Use mode h/vdisplay fields to hide out of bounds HW cursor
ARM: 8658/1: uaccess: fix zeroing of 64-bit get_user()
...
Diffstat (limited to 'arch/x86/include/asm/microcode_intel.h')
| -rw-r--r-- | arch/x86/include/asm/microcode_intel.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h index 195becc6f780..e793fc9a9b20 100644 --- a/arch/x86/include/asm/microcode_intel.h +++ b/arch/x86/include/asm/microcode_intel.h @@ -52,6 +52,21 @@ struct extended_sigtable { #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) +static inline u32 intel_get_microcode_revision(void) +{ + u32 rev, dummy; + + native_wrmsrl(MSR_IA32_UCODE_REV, 0); + + /* As documented in the SDM: Do a CPUID 1 here */ + native_cpuid_eax(1); + + /* get the current revision from MSR 0x8B */ + native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); + + return rev; +} + #ifdef CONFIG_MICROCODE_INTEL extern void __init load_ucode_intel_bsp(void); extern void load_ucode_intel_ap(void); |
