Merge tag 'drm-rust-next-2026-10-11' of https://gitlab.freedesktop.org/drm/rust/kernel into drm-next

DRM Rust changes for v7.4-rc1

- Cross-subsystem:

  - I/O (shared from driver-core tree via signed tag rust-io-7.4-rc1):

    - Reimplement register!() as a procedural macro, require matching
      base types for register access, and replace relative registers
      with typed I/O projections. Convert Nova, Tyr and the PCI sample

    - Add AsRepr/AsReprMut conversions for I/O on compatible wrapper
      types and transmute helpers with deferred size checks

  - DMA (shared from driver-core tree via signed tag rust-dma-7.4-rc1):

    - Tie Coherent, CoherentBox and CoherentHandle to the device's bound
      lifetime, and allow scoped debugfs files backed by non-'static
      data

  - Allow auxiliary registration-data closures to return covariant
    sub-fields and add UserSliceWriter::write_truncated()

  - Implement Send and Sync for MapleTree

  - Add PCI resource_flags() and IORESOURCE_MEM_64, and convert PCI IRQ
    flags to impl_flags!()

  - Add I/O view cast() with compile-time size and alignment checks

- DRM:

  - Add Rust dma_fence abstractions with separate producer (DriverFence)
    and consumer (Fence) types, per-context sequencing, signal callbacks
    and preallocation. Additional backend operations remain follow-up
    work.

  - Initialize DRM registrations and their data in place, removing a
    separate allocation

  - Drop the unused flags argument from drm::Registration::new()

- Nova:

  - UAPI and Cross Module API:
    - Add NovaCoreApi and a lifetime-bound handle for auxiliary child
      drivers, carried in nova-drm registration data
    - Expose a render node and extensible INFO ioctl reporting GPU
      architecture, opaque chip ID, usable VRAM and VRAM BAR sizes,
      full and short GPU names, and GID, with size discovery and
      truncation to the userspace buffer size
    - Move BAR-size queries into GPU info, removing GETPARAM and
      changing the UAPI

  - PRAMIN access:
    - Add typed CPU access to VRAM through the movable 1 MiB BAR0
      PRAMIN window, with per-architecture support from Turing through
      Blackwell
    - Add GpuMm centralized memory manager, VramAddress type, aperture
      documentation and optional probe-time self-tests under
      CONFIG_NOVA_CORE_SELFTESTS

  - GPU virtual memory and BAR1:
    - Add VRAM buddy allocation, TLB flushing, MMU v2/v3 page-table
      types with trait-based generics (PteOps, PdeOps, DualPdeOps,
      MmuConfig) and a generic walker
    - Add maple-tree virtual address tracking and multi-page mapping,
      separating allocation from mapping execution
    - Add CPU access to mapped VRAM through BAR1 and memory-management
      self-tests; handle 64-bit BAR0 when locating BAR1

  - GPU interrupts and GSP events:
    - Add GIN (GPU Interrupt and Notification) interrupt-tree support
      with MSI-X, MSI fallback and per-architecture rearming
    - Drain GSP events between commands via a threaded SWGEN0 handler
    - Report OS errors, robust-channel notifications and unknown
      messages without aborting command waits; hold the queue lock and
      use one deadline per wait
    - Disable GSP event interrupts on persistent falcon faults or
      drain errors
    - Add a delivery/rearm self-test, interrupt-tree KUnit coverage
      and interrupt-controller documentation

  - GSP messaging fixes:
    - Queue setup RPCs before GSP-RM boot
    - Correct DMA barriers in both queue directions

  - Firmware and transport:
    - Extract a reusable radix3 buffer mapper; zero-pad page-table
      levels to whole pages to prevent booter reads of stale padding
    - Correct GSP-FMC naming and boot-flow documentation
    - Set MCTP header version 1 for FSP messages and retain the
      command queue's BAR0 reference

  - Resource handling:
    - Replace unnecessary BarUser reference counting with in-place
      ownership and borrowed access; consolidate probe initialization
    - Declare an unlimited DMA maximum segment size

- Tyr:

  - Use bitfield!() for firmware section flags and memory attributes
    that do not describe registers

  - Zero unsupported and newly added GPU-info fields, and limit the
    doorbell array to 17 entries to fit the mapped register region

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: "Danilo Krummrich" <dakr@kernel.org>
Link: https://patch.msgid.link/DM371PN4TBJT.3LY1B0EYWSI4@kernel.org

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