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authorPrashant Gaikwad <pgaikwad@nvidia.com>2011-06-29 10:52:53 +0530
committerManish Tuteja <mtuteja@nvidia.com>2011-06-30 04:35:26 -0700
commitc8990b1f0ab269292f25343191e79f86bff93c96 (patch)
tree0a2b04efda27648e7bd7f8ab7b9905deefede387 /arch
parent1a4ca0c95e67c59ee4bac0ad66ee71cc6ee93398 (diff)
ARM: tegra: clock: Update bus operations
Relaxed bus set rate success condition: instead of exact rate require closest rate below the request (makes bus clocks configurable from sources/PLLs with variable frequencies). Bug 821534 Change-Id: I491f8841cf2ca206a54beb1c24c84f470d08eb4b Reviewed-on: http://git-master/r/38868 Reviewed-by: Manish Tuteja <mtuteja@nvidia.com> Tested-by: Manish Tuteja <mtuteja@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 39987f4dd0c2..bf92cee1aa3e 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -540,7 +540,7 @@ static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
unsigned long parent_rate = clk_get_rate(c->parent);
int i;
for (i = 1; i <= 4; i++) {
- if (rate == parent_rate / i) {
+ if (rate >= parent_rate / i) {
val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
val |= (i - 1) << c->reg_shift;
clk_writel(val, c->reg);