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authorHeiko Stuebner <heiko@sntech.de>2025-11-04 00:49:26 +0100
committerHeiko Stuebner <heiko@sntech.de>2025-11-06 00:24:48 +0100
commite06a419eaab9cee7cd5bbb0cfcfbe49e443a9d75 (patch)
tree287f6cdeed29a064aa101aee602947b2a1711555 /arch
parentff8912700f31782021ec28c530de1482fa99eab3 (diff)
arm64: dts: rockchip: add missing clocks for cpu cores on rk356x
All cpu cores are supplied by the same clock, but all except the first core are missing that clocks reference - add the missing ones. Reviewed-by: Diederik de Haas <diederik@cknow-tech.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/20251103234926.416137-4-heiko@sntech.de
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk356x-base.dtsi3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index 60adc3897fd5..d0dc7f8d0351 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -69,6 +69,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
#cooling-cells = <2>;
enable-method = "psci";
i-cache-size = <0x8000>;
@@ -84,6 +85,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
#cooling-cells = <2>;
enable-method = "psci";
i-cache-size = <0x8000>;
@@ -99,6 +101,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
#cooling-cells = <2>;
enable-method = "psci";
i-cache-size = <0x8000>;