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authorMark Brown <broonie@kernel.org>2025-09-12 00:54:56 +0100
committerMark Brown <broonie@kernel.org>2025-09-12 00:54:56 +0100
commit9ca01e9226dbbb523b49b4e583e1d522977b4fe6 (patch)
tree630b0bbaf8c27dfb24c42570ec6e399700a4e662 /drivers/acpi/riscv/cppc.c
parent2c625f0fe2db4e6a58877ce2318df3aa312eb791 (diff)
parent6a129b2ca5c533aec89fbeb58470811cc4102642 (diff)
support for Amlogic SPI Flash Controller IP
Merge series from Xianwei Zhao <xianwei.zhao@amlogic.com>: This Flash Controller is derived by adding an SPI path to the original raw NAND controller. This controller supports two modes: raw mode and SPI mode. The raw mode has already been implemented in the community (drivers/mtd/nand/raw/meson_nand.c). This submission supports the SPI mode. Add the drivers and bindings corresponding to the SPI Flash Controller.
Diffstat (limited to 'drivers/acpi/riscv/cppc.c')
-rw-r--r--drivers/acpi/riscv/cppc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/acpi/riscv/cppc.c b/drivers/acpi/riscv/cppc.c
index 440cf9fb91aa..42c1a9052470 100644
--- a/drivers/acpi/riscv/cppc.c
+++ b/drivers/acpi/riscv/cppc.c
@@ -119,7 +119,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
*val = data.ret.value;
- return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ return data.ret.error;
}
return -EINVAL;
@@ -148,7 +148,7 @@ int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
- return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+ return data.ret.error;
}
return -EINVAL;