diff options
| author | Neil Armstrong <neil.armstrong@linaro.org> | 2024-04-03 09:46:33 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2024-04-10 09:46:21 +0200 |
| commit | bb5aa08572b5313157c093a09d53ebf2efda3dc1 (patch) | |
| tree | 16066ebadb1c4e1ef1506d9b82e720813ca4d878 /drivers/clk/meson/Makefile | |
| parent | 16182ac30a68204aeb9fb373f5cb53f995251e85 (diff) | |
clk: meson: add vclk driver
The VCLK and VCLK_DIV clocks have supplementary bits.
The VCLK gate has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented in
the gate enable callback.
The VCLK_DIV clocks as enable and reset bits used to disable
and reset the divider, associated with CLK_SET_RATE_GATE it ensures
the rate is set while the divider is disabled and in reset mode.
The VCLK_DIV enable bit isn't implemented as a gate since it's part
of the divider logic and vendor does this exact sequence to ensure
the divider is correctly set.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/Makefile')
| -rw-r--r-- | drivers/clk/meson/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 9ee4b954c896..9ba43fe7a07a 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o +obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o # Amlogic Clock controllers |