diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2025-06-23 16:37:00 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2025-06-30 11:11:36 +0200 |
| commit | 328d4a7eb07389157fca1c282ecae63406a2c293 (patch) | |
| tree | 1ce77ea8ff1685e51c7ec5cfebd655fbf6a98d0e /drivers/clk/meson/a1-peripherals.h | |
| parent | 301b96e0668a6a0770a334b7243858b4f2d05091 (diff) | |
clk: amlogic: remove unnecessary headers
Some Amlogic clock controller drivers have a dedicated headers file, some
do not. Over time, these headers have evolved and now only carry register
offset definitions. These offsets are only used by the related controller
and are not meant to be shared.
These headers are not serving any purpose now.
Start enforcing some consistency between the different Amlogic clock
drivers and move the register offset definitions to the related driver.
Link: https://lore.kernel.org/r/20250623-clk-meson-no-headers-v1-1-468161a7279e@baylibre.com
[jbrunet: checkpatch strict: removed extra blank line]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/a1-peripherals.h')
| -rw-r--r-- | drivers/clk/meson/a1-peripherals.h | 46 |
1 files changed, 0 insertions, 46 deletions
diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peripherals.h deleted file mode 100644 index 26de8530184a..000000000000 --- a/drivers/clk/meson/a1-peripherals.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Amlogic A1 Peripherals Clock Controller internals - * - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Jian Hu <jian.hu@amlogic.com> - * - * Copyright (c) 2023, SberDevices. All Rights Reserved. - * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> - */ - -#ifndef __A1_PERIPHERALS_H -#define __A1_PERIPHERALS_H - -/* peripherals clock controller register offset */ -#define SYS_OSCIN_CTRL 0x0 -#define RTC_BY_OSCIN_CTRL0 0x4 -#define RTC_BY_OSCIN_CTRL1 0x8 -#define RTC_CTRL 0xc -#define SYS_CLK_CTRL0 0x10 -#define SYS_CLK_EN0 0x1c -#define SYS_CLK_EN1 0x20 -#define AXI_CLK_EN 0x24 -#define DSPA_CLK_EN 0x28 -#define DSPB_CLK_EN 0x2c -#define DSPA_CLK_CTRL0 0x30 -#define DSPB_CLK_CTRL0 0x34 -#define CLK12_24_CTRL 0x38 -#define GEN_CLK_CTRL 0x3c -#define SAR_ADC_CLK_CTRL 0xc0 -#define PWM_CLK_AB_CTRL 0xc4 -#define PWM_CLK_CD_CTRL 0xc8 -#define PWM_CLK_EF_CTRL 0xcc -#define SPICC_CLK_CTRL 0xd0 -#define TS_CLK_CTRL 0xd4 -#define SPIFC_CLK_CTRL 0xd8 -#define USB_BUSCLK_CTRL 0xdc -#define SD_EMMC_CLK_CTRL 0xe0 -#define CECA_CLK_CTRL0 0xe4 -#define CECA_CLK_CTRL1 0xe8 -#define CECB_CLK_CTRL0 0xec -#define CECB_CLK_CTRL1 0xf0 -#define PSRAM_CLK_CTRL 0xf4 -#define DMC_CLK_CTRL 0xf8 - -#endif /* __A1_PERIPHERALS_H */ |