diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2025-07-23 15:38:10 -0500 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-07-26 23:49:18 -0700 |
| commit | 264200cc3a87d5c53bfa817227624fa2bae6b2c3 (patch) | |
| tree | 5436ce1f8c92cda4f6dc7a92ce9163c8c167480a /drivers/clk/meson/g12a.c | |
| parent | 65df390bc2a7351c4bca123c62e853b35a215297 (diff) | |
clk: Fix typos
Fix typos, mostly in comments except CLKGATE_SEPERATED_* (definition and
uses updated).
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20250723203819.2910289-1-helgaas@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/meson/g12a.c')
| -rw-r--r-- | drivers/clk/meson/g12a.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index d9e546e006d7..72767bc44715 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -2489,7 +2489,7 @@ static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = { /* * Following these parent clocks, we should also have had mpll2, mpll3 * and gp0_pll but these clocks are too precious to be used here. All - * the necessary rates for MMC and NAND operation can be acheived using + * the necessary rates for MMC and NAND operation can be achieved using * g12a_ee_core or fclk_div clocks */ }; @@ -3753,8 +3753,8 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel = { }; /* - * FIXME: Force as bypass by forcing a single /1 table entry, and doensn't on boot value - * when setting a clock whith this node in the clock path, but doesn't garantee the divider + * FIXME: Force as bypass by forcing a single /1 table entry, and doesn't on boot value + * when setting a clock with this node in the clock path, but doesn't guarantee the divider * is at /1 at boot until a rate is set. */ static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] = { |