diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-09-22 18:18:55 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-09-22 18:18:55 -0700 |
| commit | 9478303619bc87c575e894d867049b25f33bf124 (patch) | |
| tree | e3f36c3b64fb24624f065bc47d53eb6996e3769d /drivers/clk/qcom/gcc-ipq806x.c | |
| parent | e2519c2c85c376666c96705239c5c7d1aef14b2d (diff) | |
| parent | 8ce8ebeb572d70e672a8d158e93ffaac80ea7576 (diff) | |
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock layer fixes from Mike Turquette:
"The fixes for the clock tree are mostly run-time bugs in clock
drivers.
The fixes for TI DRA7 remove divide-by-zero errors. The recently
merged AT91 clock driver fixes some bad error checking and the QCOM
driver fix restores audio for that platform, a clear regression. A
list iteration bug in the framework core was hit recently and is fixed
up here. Finally a compilation warning is fixed for efm32gg, which is
also a regression fix"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk/efm32gg: fix dt init prototype
clk: prevent erronous parsing of children during rate change
clk: rockchip: Fix the clocks for i2c1 and i2c2
clk: qcom: Fix sdc 144kHz frequency entry
clk: at91: fix num_parents test in at91sam9260 slow clk implementation
clk: ti: dra7-atl: Provide error check for incoming parameters in set_rate
clk: ti: divider: Provide error check for incoming parameters in set_rate
Diffstat (limited to 'drivers/clk/qcom/gcc-ipq806x.c')
| -rw-r--r-- | drivers/clk/qcom/gcc-ipq806x.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 4032e510d9aa..3b83b7dd78c7 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -1095,7 +1095,7 @@ static struct clk_branch prng_clk = { }; static const struct freq_tbl clk_tbl_sdc[] = { - { 144000, P_PXO, 5, 18,625 }, + { 200000, P_PXO, 2, 2, 125 }, { 400000, P_PLL8, 4, 1, 240 }, { 16000000, P_PLL8, 4, 1, 6 }, { 17070000, P_PLL8, 1, 2, 45 }, |