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authorDave Airlie <airlied@redhat.com>2025-11-18 06:58:01 +1000
committerDave Airlie <airlied@redhat.com>2025-11-18 07:01:26 +1000
commitf3a1d69f9b388271986f4efe1fd775df15b443c1 (patch)
treeb82a68c63a88b24b30ede3b4263fb3d2f2b6344d /drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
parentfd1a11ea111b083aa3d19f36516ecda5efa2b69f (diff)
parentccd3b4c7c37fbbd3e5244d3c54ca24ae0a37810d (diff)
Merge tag 'amd-drm-next-6.19-2025-11-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.19-2025-11-14: amdgpu: - RAS updates - GC12 DCC P2P fix - Documentation fixes - Power limit code cleanup - Userq updates - VRR fix - SMART OLED support - DSC refactor for DCN 3.5 - Replay updates - DC clockgating updates - HDCP refactor - ISP fix - SMU 13.0.12 updates - JPEG 5.0.1 fix - VCE1 support - Enable DC by default on SI - Refactor CIK and SI enablement - Enable amdgpu by default for CI dGPUs - XGMI fixes - SR-IOV fixes - Memory allocation critical path fixes - Enable amdgpu by default on SI dGPUs amdkfd: - Relax checks on save area overallocations - Fix GPU mappings after prefetch radeon: - Refactor CIK and SI enablement Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20251114192553.442621-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c12
1 files changed, 2 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 9777c5c9cb26..838a51b6098b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -188,7 +188,6 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
struct amdgpu_job *job;
void *cpu_addr;
uint64_t flags;
- unsigned int i;
int r;
BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
@@ -255,16 +254,9 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
} else {
- dma_addr_t dma_address;
-
- dma_address = mm_cur->start;
- dma_address += adev->vm_manager.vram_base_offset;
+ u64 pa = mm_cur->start + adev->vm_manager.vram_base_offset;
- for (i = 0; i < num_pages; ++i) {
- amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
- flags, cpu_addr);
- dma_address += PAGE_SIZE;
- }
+ amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr);
}
dma_fence_put(amdgpu_job_submit(job));