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authorNicholas Carbones <ncarbone@amd.com>2026-01-06 17:35:51 -0500
committerAlex Deucher <alexander.deucher@amd.com>2026-02-03 16:40:10 -0500
commit08a01ec306dbd0e096be8ee0cebb0e6a3b5fa413 (patch)
treeea7286a86faaf3effaa974a0cba790da842ff17e /drivers/gpu/drm/amd/display/dc/dml
parent9d6bd60695806782bec8562ab73aefafce067f05 (diff)
drm/amd/display: Add Gfx Base Case For Linear Tiling Handling
[Why] Post-driver cases always use linear tiling yet there is no dedicated Gfx handling for this condition. [How] Add DcGfxBase/DalGfxBase to gfx version enums and set tiling to linear when it is used. Also, enforce the use of proper tiling format as tiling information is used. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Carbones <ncarbone@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
index 74962791302f..71eeee02c0fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -1006,6 +1006,7 @@ bool dcn_validate_bandwidth(
v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
pipe->plane_state->format);
+ ASSERT(pipe->plane_state->tiling_info.gfxversion == DcGfxVersion9);
v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
pipe->plane_state->tiling_info.gfx9.swizzle);
v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);