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authorWenjing Liu <wenjing.liu@amd.com>2024-04-08 13:32:53 -0400
committerAlex Deucher <alexander.deucher@amd.com>2024-05-08 15:17:03 -0400
commit176278d8bff2c2be000b9c9509a7fc8120b5278d (patch)
tree01049fadbf592cea66a1d51928aba0627165e759 /drivers/gpu/drm/amd/display/dc/optc
parent3706bf2eba8d90887bdb7e05f9227686848e1342 (diff)
drm/amd/display: reset DSC clock in post unlock update
[why] Switching between DSC clock or disable DSC block are not double buffered update. Corruption is observed if these updates happen before DSC double buffered disconnection. [how] Move DSC disable and refclk reset to post unlock update. Wait for DSC double buffered disconnection and all mpccs are disconnected before reset DSC clock. Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/optc')
-rw-r--r--drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
index fd030e5b9de6..099658bcd77f 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
@@ -456,6 +456,7 @@ static struct timing_generator_funcs dcn401_tg_funcs = {
.set_dwb_source = NULL,
.set_odm_bypass = optc401_set_odm_bypass,
.set_odm_combine = optc401_set_odm_combine,
+ .wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear,
.set_h_timing_div_manual_mode = optc401_set_h_timing_div_manual_mode,
.get_optc_source = optc2_get_optc_source,
.set_out_mux = optc401_set_out_mux,