diff options
| author | Michael Strauss <michael.strauss@amd.com> | 2023-12-04 16:30:39 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-05-13 09:31:21 -0400 |
| commit | 8989cb919b27cd0d2aadb7f1d144cedbb12e6fca (patch) | |
| tree | 8078eda29a0a171a4743bc96e63bec5041c15696 /drivers/gpu/drm/amd/display/include | |
| parent | 90af999835130c506e7e58482474bef3414dd9fa (diff) | |
drm/amd/display: Add early 8b/10b channel equalization test pattern sequence
[WHY]
Early EQ pattern sequence is required for some LTTPR + old dongle
combinations.
[HOW]
If DP_EARLY_8B10B_TPS2 chip cap is set, this new sequence programs phy
to output TPS2 before initiating link training and writes TPS1 to
LTTPR training pattern register as instructed by vendor.
Add function to get embedded LTTPR target address offset.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: TungYu Lu <tungyu.lu@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/link_service_types.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h index 1867aac57cf2..da74ed66c8f9 100644 --- a/drivers/gpu/drm/amd/display/include/link_service_types.h +++ b/drivers/gpu/drm/amd/display/include/link_service_types.h @@ -89,6 +89,8 @@ struct link_training_settings { bool enhanced_framing; enum lttpr_mode lttpr_mode; + bool lttpr_early_tps2; + /* disallow different lanes to have different lane settings */ bool disallow_per_lane_settings; /* dpcd lane settings will always use the same hw lane settings |