diff options
| author | Ovidiu Bunea <ovidiu.bunea@amd.com> | 2025-10-02 17:47:36 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-10-20 18:21:59 -0400 |
| commit | e6c0e853f08a04d399b366640ad142ba2a7b3175 (patch) | |
| tree | 978ed9a2a79945384c37f5fd5e066718b0aee138 /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | d745900b40cc688d71c7e5de3a56acd65e4214f9 (diff) | |
drm/amd/display: Move all DCCG RCG into HWSS root_clock_control
[why & how]
Enabling/disabling DCCG RCG should be done as a last-level step when
enabling/disable blocks. This is handled by HWSS root_clock_control
already during optimize_bandwidth.
However, dccg35_dpp_root_clock_control was missing the RCG enable
call on the disable path.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
0 files changed, 0 insertions, 0 deletions