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authorLinus Probert <linus.probert@gmail.com>2026-04-03 10:22:06 +0200
committerAlex Deucher <alexander.deucher@amd.com>2026-04-03 14:04:43 -0400
commit2d23661764450fc37208c2888c91fa320e830d63 (patch)
treec40654bfe8df268d06d92c58c2f87389213cf76d /drivers/gpu/drm/amd/display
parenteea85914d15bfe3bdf9f8f80a479f0dee0aa7d73 (diff)
drm/amd/display: Replace inline NUM_ELEMENTS macro with ARRAY_SIZE
Replaces the use of local NUM_ELEMENTS macro with the ARRAY_SIZE macro defined in <linux/array_size.h>. This aligns with existing coccinelle script array_size.cocci which has been applied to other sources in order to remove inline sizeof(a)/sizeof(a[0]) patterns from other source files. Suggested-by: Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by: Linus Probert <linus.probert@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c5
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c6
2 files changed, 6 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index db86e346307c..952968ecd46e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -23,6 +23,8 @@
*
*/
+#include <linux/array_size.h>
+
#include "dm_services.h"
#include "core_types.h"
#include "timing_generator.h"
@@ -40,7 +42,6 @@
#include "dcn10/dcn10_hubbub.h"
#include "dce/dmub_hw_lock_mgr.h"
-#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
#define MAX_NUM_MCACHE 8
/* used as index in array of black_color_format */
@@ -230,7 +231,7 @@ const uint16_t *find_color_matrix(enum dc_color_space color_space,
int i;
enum dc_color_space_type type;
const uint16_t *val = NULL;
- int arr_size = NUM_ELEMENTS(output_csc_matrix);
+ int arr_size = ARRAY_SIZE(output_csc_matrix);
type = get_color_space_type(color_space);
for (i = 0; i < arr_size; i++)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 34e54fdb9d13..71a876e3dfd4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -23,6 +23,8 @@
*
*/
+#include <linux/array_size.h>
+
#include "dm_services.h"
@@ -57,8 +59,6 @@
#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
#define MAX_PLL_CALC_ERROR 0xFFFFFFFF
-#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
-
static const struct spread_spectrum_data *get_ss_data_entry(
struct dce110_clk_src *clk_src,
enum signal_type signal,
@@ -1271,7 +1271,7 @@ const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
{
int i;
- for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) {
+ for (i = 0; i < ARRAY_SIZE(video_optimized_pixel_rates); i++) {
const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i];
if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) {