diff options
| author | YuBiao Wang <YuBiao.Wang@amd.com> | 2026-07-31 13:27:38 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-10-07 12:03:58 -0400 |
| commit | 5e63e435b951a287c97d2d47f075c825e5d87505 (patch) | |
| tree | 26ff4c6cf3fb5c4278d9d8a6d4b2ba08ceaafb8b /drivers/gpu/drm/amd/include/asic_reg | |
| parent | ccf9e35ed6811f2c25ba6368e7dc6481da17159d (diff) | |
drm/amdgpu/gfx12: read xccs-per-xcp from RLC_IMU_AID_CONFIG for VFI
gfx_v12_1_get_xccs_per_xcp() supplies the compute partition layout that
gfx_v12_1_cp_resume() needs on a VF. Once VFI is enabled the VF reaches
registers through RLCG, which cannot access the GFX_IMU registers, so the
GFX_IMU_PARTITION_SWITCH read stops working. Take the same field from
RLC_IMU_AID_CONFIG instead, and read it with a direct MMIO access rather
than RREG32_SOC15, which would route back into the RLCG path.
Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h index dbd497d9fac1..249ffb38c05a 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h @@ -6649,6 +6649,8 @@ #define regRLC_IMU_MISC_BASE_IDX 1 #define regRLC_IMU_RESET_VECTOR 0x4e17 #define regRLC_IMU_RESET_VECTOR_BASE_IDX 1 +#define regRLC_IMU_AID_CONFIG 0x4e18 +#define regRLC_IMU_AID_CONFIG_BASE_IDX 1 // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcsdec diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h index 68dfafd8d027..f4a21a8c4e1b 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h @@ -20866,6 +20866,10 @@ #define RLC_IMU_RESET_VECTOR__VECTOR_MASK 0x000000FCL #define RLC_IMU_RESET_VECTOR__RESERVED_MASK 0xFFFFFF00L +//RLC_IMU_AID_CONFIG +#define RLC_IMU_AID_CONFIG__TOTAL_XCCS_IN_XCP__SHIFT 0x2 +#define RLC_IMU_AID_CONFIG__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL + // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcsdec //RLC_RLCS_DEC_START |