diff options
| author | Lijo Lazar <lijo.lazar@amd.com> | 2026-08-04 11:43:04 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-08-25 18:41:52 -0400 |
| commit | 6028808e373c2da6025c2a09403cb7f71bbf317c (patch) | |
| tree | 70fc5fa8d2b032f6a2e0cb7639344dee5165ff13 /drivers/gpu/drm/amd/include/asic_reg | |
| parent | ae6552ed047ddbbac335179e717e682b12e48695 (diff) | |
drm/amdgpu: Use partition switch shadow register
Control register is access restricted. Use the read-only copy to read
the partition settings.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h index 025e5490e6f1..dbd497d9fac1 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h @@ -7369,6 +7369,8 @@ #define regGFX_IMU_TIMER1_VALUE 0x40d1 #define regGFX_IMU_TIMER1_VALUE_BASE_IDX 1 #define regGFX_IMU_FUSE_CTRL 0x40e0 +#define regGFX_IMU_PARTITION_SWITCH_SHADOW 0x40f8 +#define regGFX_IMU_PARTITION_SWITCH_SHADOW_BASE_IDX 1 #define regGFX_IMU_FUSE_CTRL_BASE_IDX 1 #define regGFX_IMU_D_RAM_ADDR 0x40fc #define regGFX_IMU_D_RAM_ADDR_BASE_IDX 1 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h index 1cf890de35cb..68dfafd8d027 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h @@ -23556,7 +23556,9 @@ //GFX_IMU_I_RAM_DATA #define GFX_IMU_I_RAM_DATA__DATA__SHIFT 0x0 #define GFX_IMU_I_RAM_DATA__DATA_MASK 0xFFFFFFFFL - +//GFX_IMU_PARTITION_SWITCH_SHADOW +#define GFX_IMU_PARTITION_SWITCH_SHADOW__TOTAL_XCCS_IN_XCP__SHIFT 0x2 +#define GFX_IMU_PARTITION_SWITCH_SHADOW__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL // addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmhdec //GRBMH_CNTL |