diff options
| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2026-05-16 21:34:45 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-08-25 18:42:10 -0400 |
| commit | 46848df41bd369f08f3a95dc05fecfd8b6403160 (patch) | |
| tree | b8976b2e355984d2632c870dac5b18c7429ba41a /drivers/gpu/drm/amd/include | |
| parent | 81a49829ede411cc667f3a7f92dd6c1c2f38fca1 (diff) | |
drm/amdgpu: Add gc_info_v1_5 table for soc_v1_0
Initialize amdgpu_gfx_config using values from
gc_info_v1_5.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/discovery.h | 125 |
1 files changed, 86 insertions, 39 deletions
diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h index 76c9f951bc1c..575705653e95 100644 --- a/drivers/gpu/drm/amd/include/discovery.h +++ b/drivers/gpu/drm/amd/include/discovery.h @@ -272,45 +272,92 @@ struct gc_info_v1_2 { }; struct gc_info_v1_3 { - struct gpu_info_header header; - uint32_t gc_num_se; - uint32_t gc_num_wgp0_per_sa; - uint32_t gc_num_wgp1_per_sa; - uint32_t gc_num_rb_per_se; - uint32_t gc_num_gl2c; - uint32_t gc_num_gprs; - uint32_t gc_num_max_gs_thds; - uint32_t gc_gs_table_depth; - uint32_t gc_gsprim_buff_depth; - uint32_t gc_parameter_cache_depth; - uint32_t gc_double_offchip_lds_buffer; - uint32_t gc_wave_size; - uint32_t gc_max_waves_per_simd; - uint32_t gc_max_scratch_slots_per_cu; - uint32_t gc_lds_size; - uint32_t gc_num_sc_per_se; - uint32_t gc_num_sa_per_se; - uint32_t gc_num_packer_per_sc; - uint32_t gc_num_gl2a; - uint32_t gc_num_tcp_per_sa; - uint32_t gc_num_sdp_interface; - uint32_t gc_num_tcps; - uint32_t gc_num_tcp_per_wpg; - uint32_t gc_tcp_l1_size; - uint32_t gc_num_sqc_per_wgp; - uint32_t gc_l1_instruction_cache_size_per_sqc; - uint32_t gc_l1_data_cache_size_per_sqc; - uint32_t gc_gl1c_per_sa; - uint32_t gc_gl1c_size_per_instance; - uint32_t gc_gl2c_per_gpu; - uint32_t gc_tcp_size_per_cu; - uint32_t gc_tcp_cache_line_size; - uint32_t gc_instruction_cache_size_per_sqc; - uint32_t gc_instruction_cache_line_size; - uint32_t gc_scalar_data_cache_size_per_sqc; - uint32_t gc_scalar_data_cache_line_size; - uint32_t gc_tcc_size; - uint32_t gc_tcc_cache_line_size; + struct gpu_info_header header; + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; + uint32_t gc_num_tcp_per_sa; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_tcps; + uint32_t gc_num_tcp_per_wpg; + uint32_t gc_tcp_l1_size; + uint32_t gc_num_sqc_per_wgp; + uint32_t gc_l1_instruction_cache_size_per_sqc; + uint32_t gc_l1_data_cache_size_per_sqc; + uint32_t gc_gl1c_per_sa; + uint32_t gc_gl1c_size_per_instance; + uint32_t gc_gl2c_per_gpu; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_tcp_cache_line_size; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_instruction_cache_line_size; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_line_size; + uint32_t gc_tcc_size; + uint32_t gc_tcc_cache_line_size; +}; + +struct gc_info_v1_5 { + struct gpu_info_header header; + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; + uint32_t gc_num_tcp_per_sa; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_tcps; + uint32_t gc_num_tcp_per_wpg; + uint32_t gc_tcp_l1_size; + uint32_t gc_num_sqc_per_wgp; + uint32_t gc_l1_instruction_cache_size_per_sqc; + uint32_t gc_l1_data_cache_size_per_sqc; + uint32_t gc_gl1c_per_sa; + uint32_t gc_gl1c_size_per_instance; + uint32_t gc_gl2c_per_gpu; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_tcp_cache_line_size; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_instruction_cache_line_size; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_line_size; + uint32_t gc_tcc_size; + uint32_t gc_tcc_cache_line_size; + uint32_t gc_num_wgp0_per_sa1; + uint32_t gc_num_wgp1_per_sa1; + uint32_t gc_max_num_residency_ways; + uint32_t gc_cache_ways_size_in_bytes; + uint32_t gc_reserved; }; struct gc_info_v2_0 { |